Paper Info
Title
High Frequency Trading Acceleration Using FPGAs
Abstract
This paper presents the design of an application specific hardware for accelerating High Frequency Trading applications. It is optimized to achieve the lowest possible latency for interpreting market data feeds and hence enable minimal round-trip times for executing electronic stock trades. The implementation described in this work enables hardware decoding of Ethernet, IP and UDP as well as of the FAST protocol which is a common protocol to transmit market feeds. For this purpose, we developed a microcode engine with a corresponding instruction set as well as a compiler which enables the flexibility to support a wide range of applied trading protocols. The complete system has been implemented in RTL code and evaluated on an FPGA. Our approach shows a 4x latency reduction in comparison to the conventional Software based approach.
Year
DOI
Venue
2011
10.1109/FPL.2011.64
FPL
Keywords
Field
DocType
high frequency trading application,lowest possible latency,rtl code,market data,latency reduction,fast protocol,applied trading protocol,application specific hardware,high frequency trading acceleration,complete system,common protocol,low latency,application specific integrated circuits,high frequency trading,fast,udp,round trip time,fpga,local area networks,ethernet,high frequency,field programmable gate arrays,transport protocols
Microcode,High-frequency trading,Computer science,Instruction set,Field-programmable gate array,Real-time computing,Compiler,Software,Ethernet,Latency (engineering),Embedded system
Conference
Citations 
PageRank 
References 
17
1.22
9
Authors
3
Name
Order
Citations
PageRank
Christian Leber1252.19
Benjamin Geib2181.92
Heiner Litz37410.31