Name
Abstract | ||
|---|---|---|
High power dissipation is one of the major disadvantages of FPGAs. A main part of the power consumed is caused by glitches. This paper analyzes the effect of retiming to reduce the power dissipation of a Xilinx Virtex-II FPGA. The authors introduce a method to insert staging registers into large designs, that are constructed from a high abstraction level language algorithmic description. Results obtained by measurements suggest a high potential for power savings through retiming. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ECBS.2005.58 | ECBS |
Keywords | Field | DocType |
high potential,high abstraction level language,power dissipation,power consumption,high power dissipation,xilinxvirtex-ii fpga,power saving,major disadvantage,large design,algorithmic description,main part,production,application specific integrated circuits,field programmable gate arrays,fpga | Retiming,Glitch,Power optimization,Computer science,Dissipation,Field-programmable gate array,Real-time computing,Abstraction layer,Reconfigurable computing,Embedded system,Power consumption | Conference |
ISBN | Citations | PageRank |
0-7695-2308-0 | 5 | 0.47 |
References | Authors | |
7 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Robert Fischer | 1 | 5 | 0.47 |
| Klaus Buchenrieder | 2 | 125 | 18.89 |
| Ulrich Nageldinger | 3 | 112 | 15.70 |