Paper Info
Title
Abstract Application Modeling for System Design Space Exploration
Abstract
The increasing complexity of System-on-Chip (SoC) requires a complete reexamination of design and validation methods prior to final implementation whereas faster system design space exploration is today's requirement to speed up the design process in order to cope with 'timeto- market' constraint. We have introduced SoC modeling approach which mixes simulation and formal modeling and verification methods for efficient design space exploration phase of SoC design cycle. The applications are described as a network of communicating tasks whose behaviors are abstracted. Because applications are abstract, it is possible to significantly increase the speed of simulation, to perform a quick performance analysis and apply static formal analysis techniques at higher level of abstraction. The proposed methodology has been employed in the design of a telecommunication system. A part of the application is modeled as a set of tasks in a modeling language and their behavior is monitored as a waveform of events in a simulation environment.
Year
DOI
Venue
2006
10.1109/DSD.2006.19
Dubrovnik
Keywords
Field
DocType
formal modeling,soc modeling approach,faster system design space,efficient design space exploration,quick performance analysis,system design space exploration,abstract application modeling,modeling language,design process,simulation environment,static formal analysis technique,soc design cycle,formal verification,integrated circuit design,simulation,system design,logic design,system on chip
Logic synthesis,System on a chip,Computer science,Modeling language,Systems design,Real-time computing,Integrated circuit design,Engineering design process,Design space exploration,Formal verification
Conference
ISBN
Citations 
PageRank 
0-7695-2609-8
7
0.67
References 
Authors
8
5
Name
Order
Citations
PageRank
Muhammad Waseem1427.23
Ludovic Apvrille213622.23
Rabea Ameur-Boulifa381.70
Sophie Coudert4193.14
Renaud Pacalet526024.51