Paper Info
Title
A 0.5-8.5 GHz fully differential CMOS distributed amplifier
Abstract
A fully integrated fully differential distributed amplifier with 5.5 dB pass-band gain and 8.5 GHz unity-gain bandwidth is described. The fully differential CMOS circuit topology yields wider bandwidth than its single-ended counterpart, by eliminating the source degeneration effects of parasitic interconnect, bond wire, and package inductors. A simulated annealing CAD tool underpins the parasitic-aware methodology used to optimize the design including all on-chip active and passive device and off-chip package parasitics. Mixed-mode S-parameter measurement techniques used for fully differential circuit testing are reviewed. Integrated in 1.3×2.2 mm2 in a standard 0.6 μm CMOS process, the distributed amplifier dissipates 216 mW from a single 3 V supply.
Year
DOI
Venue
2002
10.1109/JSSC.2002.800960
Solid-State Circuits, IEEE Journal of
Keywords
DocType
Volume
cmos analogue integrated circuits,5.5 db,package inductor,bond wire,design optimization,source degeneration,0.5 to 8.5 ghz,s-parameters,mixed-mode s-parameter measurement,distributed amplifiers,circuit optimisation,pass-band gain,cad tool,8.5 ghz,0.6 micron,circuit cad,integrated circuit design,parasitic-aware methodology,wideband amplifiers,parasitic interconnect,radiofrequency amplifiers,fully-integrated fully-differential cmos distributed amplifier,simulated annealing,3 v,216 mw,unity-gain bandwidth,gain,packaging,bandwidth,inductors,unity gain bandwidth,s parameters,circuit topology
Journal
37
Issue
ISSN
Citations 
8
0018-9200
25
PageRank 
References 
Authors
4.46
2
2
Name
Order
Citations
PageRank
Hee-Tae Ahn17115.46
D. J. Allstot238976.58