Name
Title | ||
|---|---|---|
A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems |
Abstract | ||
|---|---|---|
The working set size of Java applications on embedded systems has recently been increasing, causing the Translation Lookaside Buffer (TLB) to become a serious performance bottleneck. From a thorough analysis of the SPECjvm98 benchmark suite executing on a commodity embedded system, we find TLB misses attribute from 24% to 50% of the total execution time. We explore and evaluate a wide spectrum of TLB-enhancing techniques with different combinations of software/hardware approaches, namely superpage for reducing TLB miss rates, two-level TLB and TLB prefetching for reducing both TLB miss rates and TLB miss latency, and even a no-TLB design for removing TLB overhead completely. We adapt and then in a novel way extend these approaches to fit the design space of embedded systems executing Java code. We compare these approaches, discussing their performance behavior, software/hardware complexity and constraints, especially the design implications for the application, runtime and OS.We first conclude that even with the aggressive approaches presented, there remains a performance bottleneck with the TLB. Second, in addition to facing very different design considerations and constraints for embedded systems, proven hardware techniques, such as TLB prefetching have different performance implications. Third, software based solutions, no-TLB design and superpaging, appear to be more effective in improving Java application performance on embedded systems. Finally, beyond performance, these approaches have their respective pros and cons; it is left to the system designer to make the appropriate engineering tradeoff. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1178597.1178614 | Memory System Performance and Correctness |
Keywords | Field | DocType |
performance behavior,performance bottleneck,different performance implication,serious performance bottleneck,tlb performance,java application,two-level tlb,java application performance,tlb prefetching,comprehensive study,software approach,commodity embedded system,embedded system,no-tlb design,java,translation lookaside buffer,system design,spectrum | Bottleneck,Suite,Computer science,Latency (engineering),Software,Hardware software,Java,Translation lookaside buffer,Operating system,Working set size,Embedded system | Conference |
ISBN | Citations | PageRank |
1-59593-578-9 | 3 | 0.41 |
References | Authors | |
11 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jinzhan Peng | 1 | 63 | 8.94 |
| Guei-Yuan Lueh | 2 | 401 | 37.41 |
| Gansha Wu | 3 | 107 | 9.06 |
| Xiaogang Gou | 4 | 3 | 0.41 |
| Ryan Rakvic | 5 | 151 | 8.96 |