Paper Info
Title
A Virtual Machine for Merit-Based Runtime Reconfiguration
Abstract
SRAM-based FPGAs can be quickly and repeatedly re- configured. One advantage of this flexibility is that time- multiplexing the FPGA's programmable logic can effectively increase the capacity of a resource-constrained system. Sys- tems consisting of a processor and FPGA resources, where the FPGA's programmable logic implements specific functionality to augment the processor and improve the performance of the system as a whole, are well-known (2, 10, 12, 13, 6, 4, 14). Since not all of the functionality is needed simultaneously, Run- Time Reconfiguration (RTR) has been proposed by a number of groups to increase (virtual) capacity. The prevailing reconfigu- ration policy is "on demand." The on-demand policy stipulates that if a particular func- tionality (kernel) is needed by the application, then it must be present in the programmable logic. If it is not already present, the system stalls while the necessary reconfiguration takes place. Hence, researchers have focused on reducing re- configuration latency as a means of improving system per- formance. Well-known techniques range from configuration caching (8) to configuration compression ( 5) to pre-fetching (9) and compile-time scheduling of reconfigurations ( 11). As an alternative to on-demand reconfiguration, this work advocates a merit-based reconfiguration policy. In the merit- based approach, each kernel that has a hardware implemen- tation also has a software implementation. A runtime sys- tem performs continuous profiling of the application to de- cide which hardware reconfigurations are most profitable at any given time. Such a system can minimize thrashing, keeping the set of hardware-resident functionality constant over short inter- vals while still adapting to phased behavior in the application. Consequently, the system is better able to tolerate reconfigura- tion latencies. Other related work includes the RTR system for Java sketched in (3) and the HASTE (7) unified instruction set ma- chine which can quickly move kernels between the processor and reconfigurable unit at runtime. The main contribution of this work is the exhibition of a simple "merit" heuristic that can be used to direct reconfiguration. In this synopsis we present a brief overview of our ongoing work. First, a simple online algorithm for calculating a figure- of-merit for RTR systems is formalized. Next we describe its implementation and demonstrate a working prototype. Included
Year
DOI
Venue
2005
10.1109/FCCM.2005.14
FCCM
Keywords
Field
DocType
virtual machine,merit-based runtime reconfiguration,programmable logic,field programmable gate arrays,profitability,application software,kernel,online algorithm,programmable logic devices,hardware,virtual machines,figure of merit
Online algorithm,Heuristic,Virtual machine,Profiling (computer programming),Computer science,Parallel computing,Real-time computing,Thrashing,Application software,Control reconfiguration,Embedded system,Runtime system
Conference
ISBN
Citations 
PageRank 
0-7695-2445-1
5
0.45
References 
Authors
13
2
Name
Order
Citations
PageRank
Brian Greskamp122910.92
Ron Sass2503.58