Name
Title | ||
|---|---|---|
A 20-MS/s to 40-MS/s reconfigurable pipeline ADC implemented with parallel OTA scaling |
Abstract | ||
|---|---|---|
A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design complexity, and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to the linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20 MS/s to 40 MS/s with 62 dB SNDR. The analog power varies linearly from 36 m W at 20 MS/s to 72 m W at 40 MS/s. The ADC was fabricated in 0.18-µm CMOS process and occupies a die area of 1.9 mm2. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCSII.2010.2050948 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
m w,design complexity,entire sampling rate range,optimal power consumption,parallel ota scaling,proposed adc,analog power,power scaling,critical analog node,reconfigurable pipeline,m cmos process,linear power,capacitors,pipelines,computational complexity,switches,transistors,operational amplifiers,bandwidth,cmos integrated circuits | Capacitor,Sampling (signal processing),Analog-to-digital converter,Electronic engineering,CMOS,Bandwidth (signal processing),DC bias,Transistor,Mathematics,Operational amplifier | Journal |
Volume | Issue | ISSN |
57 | 8 | 1549-7747 |
Citations | PageRank | References |
4 | 0.67 | 3 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kailash Chandrashekar | 1 | 47 | 7.21 |
| Marco Corsi | 2 | 19 | 3.61 |
| John Fattaruso | 3 | 4 | 0.67 |
| Bertan Bakkaloglu | 4 | 273 | 48.14 |