Name
Abstract | ||
|---|---|---|
In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining fault-injection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and - correction logic. We describe an easily portable approach, which can be applied to a wide variety of multi-GHz industrial designs. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/DATE.2006.244062 | DATE |
Keywords | Field | DocType |
formal method,wide variety,symbolic simulation,portable approach,formal verification approach,error detection logic,online error-detection,multi-ghz industrial design,fault-tolerant design,soft error,high level design,correction logic,logic,error detection,fault tolerant,error detection and correction,fault tolerance,formal methods,error correction,formal verification,industrial design,high level synthesis,radiation detectors,hardware,fault detection,indexing terms | Symbolic simulation,High-level design,Computer science,Fault detection and isolation,High-level synthesis,Error detection and correction,Real-time computing,Fault tolerance,Formal methods,Formal verification | Conference |
ISSN | ISBN | Citations |
1530-1591 | 3-9810801-0-6 | 28 |
PageRank | References | Authors |
1.19 | 13 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| U. Krautz | 1 | 28 | 1.19 |
| Matthias Pflanz | 2 | 76 | 8.18 |
| C. Jacobi | 3 | 55 | 3.10 |
| H. W. Tast | 4 | 28 | 1.19 |
| K. Weber | 5 | 37 | 1.79 |
| H. T. Vierhaus | 6 | 103 | 12.33 |