Name
Abstract | ||
|---|---|---|
While set-associative caches incur fewer misses than direct-mapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are probed in parallel. This paper presents the location cache structure which significantly reduces the power consumption for large set-associative caches. We propose to use a small cache, called location cache to store the location of future cache references. If there is a hit in the location cache, the supported cache is accessed as a direct-mapped cache. Otherwise, the supported cache is referenced as a conventional set-associative cache. The worst case access latency of the location cache system is the same as that of a conventional cache. The location cache is virtually indexed so that operations on it can be performed in parallel with the TLB address translation. These advantages make it ideal for L2 cache systems where traditional way-predication strategies perform poorly. We used the CACTI cache model to evaluate the power consumption and access latency of proposed cache architecture. Simplescalar CPU simulator was used to produce final results. It is shown that the proposed location cache architecture is power-efficient. In the simulated cache configurations, up-to 47% of cache accessing energy and 25% of average cache access latency can be reduced. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/LPE.2004.1349321 | international symposium on low power electronics and design |
Keywords | DocType | ISBN |
l2 cache system,conventional cache,large set-associative caches,tlb,microprocessor chips,average cache access latency,location cache,cache storage,cacti cache model,conventional set-associative cache,latency,low-power electronics,low-power l2 cache system,simplescalar cpu simulation,virtually indexed,large set-associative cache,l1/l2 caches,set-associative caches,cache architecture,data location,future cache reference,memory architecture,hardware design,content-addressable storage,cache accessing energy,reduced power consumption,location cache structure,direct-mapped cache,indexation,power efficiency,hitting time | Conference | 1-58113-929-2 |
Citations | PageRank | References |
12 | 0.65 | 26 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rui Min | 1 | 12 | 0.65 |
| Wen-Ben Jone | 2 | 419 | 46.30 |
| Yiming Hu | 3 | 639 | 44.91 |