Name
Abstract | ||
|---|---|---|
Stereo Vision, a technique aimed at inferring depth information from stereo images, has been used in a wide range of computer vision applications, with real-time requirements in emerging embedded vision systems. Computation of the disparity map, a vital step in extracting depth information from stereo images, requires a significant amount of computational resources. As such, existing software implementations require high-end hardware platforms to achieve real-time frame rates, suggesting that dedicated hardware mechanisms might be more suitable for embedded applications. In this paper, we present a disparity map computation architecture targeting embedded stereo vision applications with hard real-time requirements. The architecture integrates a hardware edge detection mechanism that reduces the search space, improving the overall performance, and is configurable in terms of various application parameters, making it suitable for a number of application environments. The paper also presents a study on the impact of the various parameters in terms of the performance and hardware/power overheads. An experimental prototype of the architecture was implemented on the Xilinx ML505 FPGA Evaluation Platform, achieving 50 Frames Per Second (fps) for 1,280 脳 1,024 image sizes. Moreover, the quality of the disparity maps generated by the proposed system is comparable to other existing hardware implementations featuring local stereo correspondence methods. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TC.2012.32 | IEEE Trans. Computers |
Keywords | Field | DocType |
disparity map computation architecture,embedded stereo vision application,disparity map,real-time disparity map computation,hardware edge detection mechanism,local stereo correspondence method,stereo image,high-end hardware platform,computer vision application,edge-directed hardware architecture,existing hardware,dedicated hardware mechanism,image processing,field programmable gate array,computer vision,field programmable gate arrays,detectors,real time systems,feature extraction,edge detection,stereo vision,image size,hardware,correlation,computer architecture | Computer science,Edge detection,Stereopsis,Field-programmable gate array,Image processing,Feature extraction,Real-time computing,Frame rate,Computer hardware,Hardware architecture,Embedded system,Computation | Journal |
Volume | Issue | ISSN |
62 | 4 | 0018-9340 |
Citations | PageRank | References |
18 | 0.96 | 17 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christos Ttofis | 1 | 62 | 5.90 |
| Stavros Hadjitheophanous | 2 | 19 | 2.32 |
| Athinodoros S. Georghiades | 3 | 2483 | 128.27 |
| Theocharis Theocharides | 4 | 205 | 26.83 |