Name
Abstract | ||
|---|---|---|
This paper presents a high-speed Forward Error Correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 10 and 40-Gb/s optical communication systems. A highspeed two-parallel RS(255, 239) decoder has been proposed and the derived structure can also be applied to implement the 10 and 40-Gb/s RS FEC architectures. The implementation results show that 16-Ch. RS FEC architecture can operate at a clock frequency of 160MHz and has a throughput of 41 Gb/s for the Xilinx Virtex4 FPGA. Also, RS FEC operates at a clock frequency of 400MHz and has a throughput of 102 Gb/s for 0.18-mu m CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1587/elex.5.374 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
Reed-Solomon code, forward error correction, two-parallel | Forward error correction,Architecture,Computer science,Optical communication,Parallel computing,Field-programmable gate array,Reed–Solomon error correction,Electronic engineering,CMOS,Throughput,Computer hardware,Clock rate | Journal |
Volume | Issue | ISSN |
5 | 10 | 1349-2543 |
Citations | PageRank | References |
14 | 1.39 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seungbeom Lee | 1 | 45 | 7.04 |
| Changseok Choi | 2 | 33 | 7.39 |
| Hanho Lee | 3 | 205 | 40.92 |