Name
Title | ||
|---|---|---|
Register Length Analysis and VLSI Optimization of VBS Hadamard Transform in H.264/AVC |
Abstract | ||
|---|---|---|
Fidelity range extensions of H.264/AVC adopt variable block size (VBS) transform techniques to employ 8 × 8/4 × 4 Hadamard transforms adaptively during the fractional motion estimation. In this literature, the hardwired VBS Hadamard transform accelerator is developed with the following contributions: 1) developed a hardware reusing scheme between 8 × 8 and 4 × 4 transforms within the architecture design; 2) devised the intermediate bit-truncation algorithm to reduce the hardware cost while maintaining the computational precision well; and 3) reduced the bit-width of sum of absolute transformed differences (SATD) value as compared to the primitive implementation, resulting in optimization in both power and hardware cost for the SATD generator implementation. With TSMC 0.18 μm CMOS technology, the experiments demonstrate that for each VBS Hadamard transform engine, 13.0-30.4% saving in hardware cost and 12.6-32.4% saving in power consumption are achieved, whereas the incurred coding quality loss is less than 0.2089 dB in terms of BDPSNR. From the aspect of the whole encoder implementation, and considering the parallelism in searching factional pixel candidates, the proposed strategies garner 2.0 3.9% overall gate count reduction. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/TCSVT.2011.2129330 | IEEE Trans. Circuits Syst. Video Techn. |
Keywords | Field | DocType |
h.264/avc,optimisation,vbs hadamard transform,cmos integrated circuits,register length analysis,hardware cost,power consumption,computational precision,primitive implementation,coding quality loss,hadamard transform,data compression,satd generator,vbs hadamard,h.264-avc,vlsi optimization,frext,intermediate bit-truncation algorithm,bdpsnr,hardwired vbs hadamard,cmos technology,tsmc,size 0.18 mum,whole encoder implementation,hadamard transforms,vlsi,video coding,satd generator implementation,vbs hadamard transform accelerator,sum of absolute transformed differences,architecture design,variable block size transform technique,variable block size,motion estimation,noise,algorithm design,indexing terms,hardware,algorithm design and analysis,error correction code,encoding,registers | Gate count,Computer science,Computational science,Artificial intelligence,Very-large-scale integration,Block size,Computer vision,Algorithm design,Algorithm,Encoder,Sum of absolute transformed differences,Data compression,Hadamard transform | Journal |
Volume | Issue | ISSN |
21 | 5 | 1051-8215 |
Citations | PageRank | References |
1 | 0.41 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhenyu Liu | 1 | 120 | 12.29 |
| Junwei Zhou | 2 | 118 | 16.64 |
| Dongsheng Wang | 3 | 373 | 64.93 |
| T. Ikenaga | 4 | 14 | 2.62 |