Name
Abstract | ||
|---|---|---|
Current trends in analog/mixed-signal design for battery-powered devices demand the adoption of cheap and power-efficient ADCs. SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/medium- bandwidth range in Craninckx, J. and Van der Plas, G., (2007). However, when the comparator determines in first instance the overall performance, as in most SAR ADCs, comparator thermal noise can limit the maximum achievable resolution. More than 1 and 2 ENOB reductions are observed in Craninckx, J. and Van der Plas, G., (2007) and Kuttner, F., (2002), respectively, because of thermal noise, and degradations could be even worse with scaled supply voltages and the extensive use of dynamic regenerative latches without pre-amplification. Unlike mismatch, random noise cannot be compensated by calibration and would finally demand a quadratic increase in power consumption unless alternative circuit techniques are devised. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISSCC.2008.4523145 | San Francisco, CA |
Keywords | DocType | ISBN |
CMOS integrated circuits,analogue-digital conversion,comparators (circuits),flip-flops,mixed analogue-digital integrated circuits,thermal noise,ENOB reductions,SAR architectures,analog/mixed-signal design,battery-powered devices,comparator thermal noise,digital CMOS,dynamic regenerative latches,noise-tolerant dynamic-SAR ADC,power consumption,random noise,supply voltages | Conference | 978-1-4244-2011-7 |
Citations | PageRank | References |
2 | 0.42 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vito Giannini | 1 | 702 | 44.60 |
| Pierluigi Nuzzo | 2 | 305 | 33.35 |
| V. Chironi | 3 | 15 | 3.96 |
| Andrea Baschirotto | 4 | 168 | 48.21 |
| Geert Van der Plas | 5 | 355 | 100.92 |
| Jan Craninckx | 6 | 756 | 181.43 |