Paper Info
Title
Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models.
Abstract
Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. One significant use case for HLMs are virtual hardware prototypes used for driver development. However, current industry practice does not fully exploit HLMs by neglecting to use them as a common executable specification for the whole design process. In this paper, we present an approach to use HLMs for enabling an early integration of hardware verification and firmware development. Via coverage measures of the HLM the approach ensures that the specification has been used consistently across the development of the hardware verification environment and the firmware under development. The hardware verification environment finally ensures that all specification requirements used by the firmware are provided by the hardware. We will show the benefits of our integrated verification approach to real-world system designs by presenting first results from modeling and simulating a network controller for the Parallel Sysplex∗ architecture used in IBM System z mainframes∗.
Year
Venue
Field
2010
MBMV
Computer architecture,Computer science,Electronic system-level design and verification,Exploit,SystemC,Design flow,Network interface controller,Computer hardware,Design process,Firmware,Embedded system,Executable
DocType
Citations 
PageRank 
Conference
2
0.39
References 
Authors
11
5
Name
Order
Citations
PageRank
Joachim Falk121517.27
Christian Zebelein2385.43
Christian Haubelt379668.77
Jürgen Teich42886273.54
Rainer Dorsch513512.60