Name
Abstract | ||
|---|---|---|
In this paper a VLSI architecture for a configurable turbo decoder, compliant with the 3GPP2 standard is presented. A simple modification of the conventional iterative structure of a turbo decoder is presented, where one of the constituent interleavers can be eliminated, allowing an important reduction in the overall complexity of the turbo decoder with no performance degradations. Performance analysis is highlighted vis \`a vis a fixed point reference model. In addition, results of the overall architecture with the sliding window approach and implemented on an Alter a device is shown. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ReConFig.2011.25 | ReConFig |
Keywords | Field | DocType |
simplified turbo decoder,performance analysis,configurable turbo decoder,vlsi architecture,performance degradation,turbo decoder,conventional iterative structure,overall complexity,constituent interleavers,fixed point reference model,overall architecture,3gpp2,measurement,reference model,turbo code,computer architecture,channel coding,systematics,fixed point,iterative methods,decoding,hardware,turbo codes,sliding window | Sliding window protocol,Reference model,Computer science,Iterative method,Turbo code,Real-time computing,Turbo equalizer,Soft-decision decoder,Fixed point,Decoding methods | Conference |
ISBN | Citations | PageRank |
978-1-4577-1734-5 | 0 | 0.34 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lennin C. Yllescas-Calderon | 1 | 3 | 0.72 |
| Adrian J. Espino-Orozco | 2 | 0 | 0.34 |
| R. Parra-Michel | 3 | 23 | 5.19 |
| Luis F. González-Perez | 4 | 3 | 0.79 |
| Yllescas-Calderon, L.C. | 5 | 0 | 0.34 |
| Espino-Orozco, A.J. | 6 | 0 | 0.34 |
| Gonzalez-Perez, L.F. | 7 | 4 | 1.45 |