Name
Abstract | ||
|---|---|---|
Periodic application of time-redundant error checking to processor arrays provides a trade-off between error detection latency and performance degradation. The goal is to achieve high error coverage while satisfying performance requirements. In this paper, we derive the optimal scheduling of checking patterns for linear processor arrays in order to minimize the error detection latency and maximize the error coverage. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1006/jpdc.1994.1142 | J. Parallel Distrib. Comput. |
Keywords | Field | DocType |
periodic concurrent error detection,processor array | Error checking,Scheduling (computing),Computer science,Parallel computing,Error detection and correction,Vector processor,Periodic graph (geometry),Error detection latency | Journal |
Volume | Issue | ISSN |
23 | 3 | Journal of Parallel and Distributed Computing |
Citations | PageRank | References |
1 | 0.37 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yi-min Wang | 1 | 3573 | 274.00 |
| Pi-yu Chung | 2 | 217 | 22.08 |
| W. Kent Fuchs | 3 | 1469 | 279.02 |