Name
Abstract | ||
|---|---|---|
The Godson-2G microprocessor is a high performance SOC which integrates a four-issue 64-bit high performance CPU core (called
GS464), a DDR2/3 controller, a HyperTransport controller, a PCI/PCI-X controller, etc. It is physically implemented in 65
nm CMOS process and reaches the frequency of 1GHz with power consumption less than 4 W. The main challenges of Godson-2G physical
implementation include nanometer process technology effects, high performance design targets, and tight schedule. This paper
describes the key innovative features of physical design methodology which had been used in Godson-2G physical implementation,
with particular emphasis on interconnect driven floorplan generation (ICD-FP), adapted boundary constraints design optimization
(ABC-OPT), automatic register group clock tree generation methodology (ARG-CTS). |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1007/s11390-010-9319-z | J. Comput. Sci. Technol. |
Keywords | Field | DocType |
computer architecture,physical design,design optimization | Control theory,Computer science,High performance design,Microprocessor,Real-time computing,Physical design,Interconnection,Multi-core processor,HyperTransport,Floorplan | Journal |
Volume | Issue | ISSN |
25 | 2 | null |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ji-Ye Zhao | 1 | 13 | 1.58 |
| Dong Liu | 2 | 2 | 1.06 |
| Dan-Dan Huan | 3 | 7 | 1.71 |
| Menghao Su | 4 | 14 | 3.16 |
| Bin Xiao | 5 | 6 | 2.31 |
| Ying Xu | 6 | 1 | 0.74 |
| Feng Shi | 7 | 14 | 2.96 |
| Chen Chen | 8 | 6 | 2.22 |
| Song Wang | 9 | 954 | 79.55 |