Paper Info
Title
Fully hardware based WFQ architecture for high-speed QoS packet scheduling
Abstract
A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing Reduced Latency DRAM (RLDRAM) II and Quad Data Rate (QDR) II SRAM memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.
Year
DOI
Venue
2012
10.1016/j.vlsi.2011.01.001
Integration
Keywords
Field
DocType
circuit architecture,high-speed qos packet scheduling,current circuit architecture,wfq algorithm computation circuit,altera stratix ii fpga,retrieval circuit,full asic implementation,ii sram memory component,full hardware implementation,wfq architecture,current implementation,scalable modular circuit design,traffic management,wfq,qos,fpga,fair queuing
Throughput (business),Stratix,Computer science,Network scheduler,Circuit design,Real-time computing,Application-specific integrated circuit,Throughput,Weighted fair queueing,Computer hardware,Embedded system,Fair queuing
Journal
Volume
Issue
ISSN
45
1
Integration, the VLSI Journal
Citations 
PageRank 
References 
4
0.47
26
Authors
5
Name
Order
Citations
PageRank
Kieran McLaughlin120822.19
Dwayne Burns2173.97
Ciaran Toal3286.99
Colm McKillen440.81
Sakir Sezer5101084.22