Name
Title | ||
|---|---|---|
Enhancing fixed point DSP processor performance by adding CPLDs as coprocessing elements |
Abstract | ||
|---|---|---|
Programmable logic provides an ideal balance between the flexibility of a DSP processor and the performance of a DSP ASIC solution. Programmable logic also provides a strong complement to a DSP processor to offload computationally intensive functions/algorithms as a DSP coprocessor. In addition to improving system performance, this coprocessor methodology also acts to protect investments that have been trade in DSP processor tools, code, and experience by extending the potential applications that could initially be done with a given DSP processor. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1007/3-540-63465-7_237 | field programmable logic and applications |
Keywords | Field | DocType |
fixed point,coprocessing element,DSP processor performance | Signal processing,Digital signal processing,Computer science,Parallel computing,Programmable logic array,Application-specific integrated circuit,Cooley–Tukey FFT algorithm,Fast Fourier transform,Coprocessor,Embedded system,Programmable logic device | Conference |
ISBN | Citations | PageRank |
3-540-63465-7 | 0 | 0.34 |
References | Authors | |
1 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| david s greenfield | 1 | 0 | 1.01 |
| Caleb Crome | 2 | 0 | 0.34 |
| Martin S. Won | 3 | 0 | 0.34 |
| Doug Amos | 4 | 0 | 0.34 |