Title
A Methodology for CMOS Low Noise Ampli.er Design
Abstract
An intuitive strategy for CMOS low noise amplifier (LNA) design, compromising noise and linearity performance optimization, is presented. Analytical expressions for noise factor and IM3 are derived. The gain and power dissipation are considered pre-fixed parameters for this approach. A 2.4 GHz LNA has been designed and simulated in a 0.35 µm CMOS technology to validate the proposed methodology.
Year
DOI
Venue
2003
10.1109/SBCCI.2003.1232800
SBCCI
Keywords
DocType
ISBN
proposed methodology,power dissipation,intuitive strategy,noise factor,Analytical expression,GHz LNA,CMOS low noise amplifier,pre-fixed parameter,m CMOS technology,CMOS Low Noise Ampli,er Design,linearity performance optimization
Conference
0-7695-2009-X
Citations 
PageRank 
References 
3
0.49
0
Authors
3
Name
Order
Citations
PageRank
Elkim Roa1124.85
João Navarro Soares2114.92
Wilhelmus Van Noije3129.16