Paper Info
Title
A Physical Design Method For A New Memory-Based Reconfigurable Architecture Without Switch Blocks
Abstract
In this paper, we propose a placement and routing method for a new memory-based programmable logic device (MPLD) and confirm its capability by placing and routing benchmark circuits. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas field programmable gate arrays (FPGAs) consist of LUTs (logic elements) and switch blocks (routing elements). MPLDs contain logic circuits more efficiently than FPGAs because of their flexibility and area efficiency. However, directly applying the existing placement and routing algorithms of FPGAs to MPLDs overcrowds the placed logic cells and causes a shortage of routing domains between logic cells. Our simulated annealing-based method considers the detailed wire congestion and nearness between logic cells based on the cost function and reserves the area for routing. In the experiments, our method reduced wire congestion and successfully placed and routed 27 out of 31 circuits, 13 of which could not be placed or routed using the versatile place and route tool (VPR), a well-known method for FPGAs.
Year
DOI
Venue
2012
10.1587/transinf.E95.D.324
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
Keywords
Field
DocType
reconfigurable device, physical design, placement, routing, MPLD, FPGA, EDA
Link-state routing protocol,Logic gate,Computer science,Static routing,Artificial intelligence,Routing (electronic design automation),Computer hardware,Programmable logic device,Computer vision,Complex programmable logic device,Parallel computing,Place and route,Logic family
Journal
Volume
Issue
ISSN
E95D
2
1745-1361
Citations 
PageRank 
References 
0
0.34
3
Authors
6
Name
Order
Citations
PageRank
M. Nakamura114930.71
Masato Inagi2316.73
Kazuya Tanigawa363.33
Tetsuo Hironaka4149.36
Masayuki Sato521.07
Takashi Ishiguro600.68