Paper Info
Title
Evaluation of a Hardware-Software Codesign Technique of Network Protocol Stacks
Abstract
Many studies in SoC (System-on-Chip) areas ignore the scheduling of messages exchanged between hardware-software components as a fine level of inter-component communication granularity. Such a message scheduling scheme in hardware-software codesign of SoC systems has received comparatively less attention in the literature despite their importance as an element of a complete partitioning solution. In this paper, we attempt to resolve a message scheduling problem to meet the semantics of inter-component communications. Additionally, we evaluate the performance of hardware-software codesign for network protocol stacks.
Year
DOI
Venue
2010
10.1109/NCA.2010.49
NCA
Keywords
Field
DocType
processor scheduling,protocols,inter-component communication,network protocol stacks,soc,message scheduling,message scheduling problem,hardware-software component,message scheduling scheme,hardware-software codesign technique,system-on-chip,hardware-software components,soc system,hardware-software codesign,fine level,inter-component communication granularity,performance evaluation,network protocol stack,network protocol,complete partitioning solution,system on a chip,software component,system on chip,hardware,real time systems,scheduling problem
Job shop scheduling,System on a chip,Stack (abstract data type),Scheduling (computing),Computer science,Software,Granularity,Semantics,Distributed computing,Communications protocol
Conference
ISBN
Citations 
PageRank 
978-1-4244-7628-2
0
0.34
References 
Authors
2
2
Name
Order
Citations
PageRank
Tae-Hoon Kim145953.02
Sung Woo Tak22314.34