Name
Abstract | ||
|---|---|---|
The paper describes the concept, architecture, and prototype test results of a packet processor that enables us to implement an application-specific high-speed packet processing system without expert-level programming skills. This processor has a pipelined processing architecture and features coarse-grained instructions that are based on the data formats of the telecommunication packet. Using this processor, target applications can be implemented within a short working period without degrading the processing performance. We implemented a prototype system to evaluate its packet propagation delay and packet forwarding performance. The measured results suggest that the architecture is useful for packet processing on high-speed telecommunication networks. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1142/S0218126607003502 | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Keywords | Field | DocType |
packet processing,active network,processor architecture | Network processor,Packet segmentation,End-to-end delay,Packet analyzer,Computer science,Packet processing,Fast packet switching,Packet generator,Processing delay,Embedded system | Journal |
Volume | Issue | ISSN |
16 | 1 | 0218-1266 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takahiro Murooka | 1 | 80 | 13.19 |
| Akira Nagoya | 2 | 141 | 17.78 |
| Toshiaki Miyazaki | 3 | 241 | 42.14 |
| Hiroyuki Ochi | 4 | 215 | 44.57 |
| Yukihiro Nakamura | 5 | 177 | 50.18 |