Name
Abstract | ||
|---|---|---|
With the advent of the deep submicron age, circuit performance is strongly impacted by process variations and the-influence oil the circuit delay to the power-supply voltage increases more and more due to CMOS feature size shrinkage. Power grid optimization which considers the timing error risk caused by the variations and IR drop becomes very important for stable and hi-speed operation of system-on-chip. Conventionally, it lot of power grid optimization algorithms have been proposed, and most of them use IR drop as their object functions. However, the IR drop is an indirect metric and we suspect that it is vague metric for the real goal of LSI design. In this paper, first, we propose an approach which uses the "timing error risk caused by IR drop" as a direct objective function. Second, the critical path map is introduced to express the existence of critical paths distributed in the entire chip. The timing error risk is decreased by using the critical path map and the new Objective function. Some experimental results show the effectiveness. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1093/ietfec/e91-a.12.3423 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
power grid optimization, timing violation, critical path, process variation, IR drop | Power network design,Control theory,Voltage,Timing error,Theoretical computer science,Chip,Real-time computing,CMOS,Optimization algorithm,Process variation,Critical path method,Mathematics | Journal |
Volume | Issue | ISSN |
E91A | 12 | 0916-8508 |
Citations | PageRank | References |
4 | 0.54 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshiyuki Kawakami | 1 | 18 | 3.07 |
| Makoto Terao | 2 | 23 | 2.04 |
| Masahiro Fukui | 3 | 42 | 14.57 |
| Shuji Tsukiyama | 4 | 85 | 19.66 |