Name
Abstract | ||
|---|---|---|
Abstract Today’s FPGAs (Field Programmable,Gate Arrays) are widely used, but not to their full potential. In Virtex series FPGAs from Xilinx a special feature, the dynamic and par- tial reconfiguration is available. This feature enables a de- signer to create a system on chip with a static area and a reconfigurable part that can be exchanged,during run-time while the remaining static portion is still operational. In this paper we present a new technique that combines the advan- tages of already existing partial dynamic,reconfiguration flows for Xilinx Virtex FPGAs. The method reduces unnec- essary frames in bitstreams without increasing their quan- tity. In our simple example design we could achieve an im- provement of the reconfiguration times up to 8 percent com- pared to a common,matchable reconfiguration method. Our approach also surpasses all Xilinx generated bitstreams in terms of reconfiguration times. |
Year | Venue | Keywords |
|---|---|---|
2006 | ARCS Workshops | field programmable gate array,system on chip |
Field | DocType | Citations |
Computer science,Virtex,Embedded system | Conference | 4 |
PageRank | References | Authors |
1.04 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christopher Claus | 1 | 221 | 20.39 |
| Florian Helmut Müller | 2 | 36 | 4.84 |
| Walter Stechele | 3 | 365 | 52.77 |