Name
Abstract | ||
|---|---|---|
In this paper, we proposed a low power digital signal processing (DSP) scheme with stochastic logic protection. The reduction of supply voltage will reduce the power consumption effectively. However, the timing violation will be happened when the voltage overscaling (VOS) is applied. Fortunately, the stochastic logic has simple hardware structure, and the critical path is short. Thus, we can use stochastic logic as the error control (EC) module to mitigate the soft error by the VOS. Compared with traditional EC based low power DSP, the proposed method can achieve higher energy efficiency with high performance. According to the case study of a 26-tap FIR filter, the stochastic logic based EC module can achieve 65% power saving within 2.5dB signal-to-noise ratio (SNR) loss, which outperforms 6dB than traditional RPR method. When the soft error for each logic gate is considered, the advantage of SFIR based system is more obvious than traditional method. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISCAS.2012.6271970 | 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) |
Keywords | Field | DocType |
low power, stochastic logic, voltage overscaling | Logic gate,Digital signal processing,Sequential logic,Pass transistor logic,Soft error,Computer science,Signal-to-noise ratio,Electronic engineering,Logic level,Low-power electronics | Conference |
Volume | Issue | ISSN |
null | null | 0271-4302 |
Citations | PageRank | References |
4 | 0.45 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jienan Chen | 1 | 84 | 13.64 |
| Jian-hao Hu | 2 | 83 | 12.99 |
| Shuyang Li | 3 | 12 | 1.78 |