Name
Abstract | ||
|---|---|---|
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-pad memories lack the complex tag checking and comparison logic, thereby proving to be efficient in area and power. In this work, we focus on exploiting scratch-pad memories for storing hot code segments within an application. Static placement techniques focus on placing the most frequently executed portions of programs into the scratch-pad. However, static schemes are inherently limited by not allowing the contents of the scratch-pad memory to change at run time. In a large fraction of applications, the instruction memory footprints exceed the scratch-pad memory size, thereby limiting the usefulness of the scratch-pad. We propose a compiler managed dynamic placement algorithm, wherein multiple hot code sequences, or traces, are overlapped with each other in the scratch-pad memory at different points in time during execution. Special copy instructions are provided to copy the traces into the scratch-pad memory at run-time. Using a power estimate, the compiler initially selects the most frequent traces in an application for relocation into the scratch-pad memory. Through iterative code motion and redundancy elimination, copy instructions are inserted in infrequently executed regions of the code. For a 64-byte code cache, the compiler managed dynamic placement achieves an average of 64% energy improvement over the static solution in a low-power embedded microcontroller. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/CGO.2005.13 | CGO |
Keywords | Field | DocType |
low power on-chip memory,multiple hot code sequence,64-byte code cache,scratch-pad memory size,copy instruction,compiler managed dynamic instruction,instruction memory footprint,low-power code cache,dynamic placement,scratch-pad memory,iterative code motion,hot code segment,switches,reduced instruction set computing,energy management,chip,software maintenance,hardware,data engineering | Dead code elimination,Computer science,Cache,Parallel computing,Code generation,Compiler,Real-time computing,Reduced instruction set computing,Redundancy (engineering),Microcontroller,Dead code | Conference |
ISSN | ISBN | Citations |
2164-2397 | 0-7695-2298-X | 27 |
PageRank | References | Authors |
1.17 | 24 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rajiv A. Ravindran | 1 | 213 | 11.13 |
| Pracheeti D. Nagarkar | 2 | 27 | 1.17 |
| Ganesh S. Dasika | 3 | 387 | 24.30 |
| Eric D. Marsman | 4 | 115 | 10.30 |
| Robert M. Senger | 5 | 294 | 23.55 |
| Scott Mahlke | 6 | 4811 | 312.08 |
| Richard B. Brown | 7 | 473 | 64.00 |