Name
Abstract | ||
|---|---|---|
We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4 bit, 1 GS/s prototypes in 0.13 mum and 65 nm CMOS processes, which show a small area (0.015 mm2) and small power consumption (<2.4 mW). |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TCSII.2009.2020947 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
cmos process,small area,digital delay-line-based adc design,analogue-digital conversion,process scaling,65-nm cmos process,jitter effect,size 65 nm,jitter,delay-line-based analog-to-digital converter,scaling,input voltage,digital block,analog-to-digital converter (adc),small power consumption,delay line,analog-to-digital converter,voltage comparators,cmos digital integrated circuits,digital delay line,delay lines,size 0.13 mum,digital code,voltage,cmos technology | 4-bit,Comparator,Voltage,Delay,Electronic engineering,CMOS,Converters,Analog-to-digital converter,Jitter,Mathematics | Journal |
Volume | Issue | ISSN |
56 | 6 | 1549-7747 |
Citations | PageRank | References |
44 | 2.85 | 10 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guansheng Li | 1 | 97 | 7.48 |
| Yahya M. Tousi | 2 | 161 | 13.68 |
| Arjang Hassibi | 3 | 122 | 25.61 |
| Ehsan Afshari | 4 | 325 | 36.65 |