Name
Abstract | ||
|---|---|---|
We present evaluation results for DC offset in the direct conversion receiver for W-CDMA with low current consumption. Measured results indicate that steady-state DC offset is suppressed to less than 30 mV and transitional variation in DC offset with gain change is limited to around 100 mV. The computer simulation revealed that negligible degradation in bit error rate (BER) performance due to the DC offset transition occurs with the proposed receiver. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1587/elex.2.434 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
direct conversion, DC offset, BER performance | Input offset voltage,Computer science,W-CDMA,Electronic engineering,Current consumption,DC bias,Electrical engineering,Direct-conversion receiver,Bit error rate | Journal |
Volume | Issue | ISSN |
2 | 15 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroshi Yoshida | 1 | 10 | 3.96 |
| Takehiko Toyoda | 2 | 1 | 1.77 |
| Tadashi Arai | 3 | 0 | 1.69 |
| Hiroshi Tsurumi | 4 | 9 | 3.34 |