Name
Abstract | ||
|---|---|---|
This paper presents a new testable allocation scheme that has been included in a high level synthesis environment to enhance the testability of the circuits synthesized. Designs obtained have small area overheads and no delays in critical timing parts of the circuit thanks to the testable structure generated by the simultaneous optimization of testability and cost during the exploration of the design space. Some heuristics are introduced that reduce the search time with no space bounding. |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1016/0165-6074(93)90102-Q | Microprocessing and Microprogramming |
Keywords | DocType | Volume |
testable allocation,data path structure,high level synthesis | Journal | 39 |
Issue | ISSN | Citations |
2-5 | Microprocessing and Microprogramming | 2 |
PageRank | References | Authors |
0.39 | 4 | 5 |