Paper Info
Title
An Architecture for Software-Based iSCSI on Multiprocessor Servers
Abstract
To achieve IP-converged cluster deployments, the performance and scalability of iSCSI must approach that of FC SANs. We recognize and quantify that the major overhead of iSCSI comes from TCP/IP processing. Industry has largely responded with TCP offload engines (TOEs) and iSCSI storage adapters. As an alternative, this paper shows a software implementation of iSCSI on generic OSes and processors. The trend towards chip multiprocessing (CMP) and integrated memory controllers (MCH) largely motivated our direction. With CMP, increased processing power is delivered through multiple cores per processor; on-die MCH allows memory bandwidth to scale better with processor speeds. Our approach and analysis shows the effectiveness of partitioning the workload suitable for a CMP system, allowing iSCSI to scale with the increasing processing power and memory bandwidth of servers over time.
Year
DOI
Venue
2005
10.1109/IPDPS.2005.89
IPDPS
Keywords
Field
DocType
multiprocessor servers,increased processing power,ip processing,memory bandwidth,tcp offload engine,cmp system,iscsi storage adapter,software-based iscsi,processor speed,on-die mch,integrated memory controller,increasing processing power,file servers,transport protocols,memory controller,search engines,ip network,web server,chip,local area networks,bandwidth,resource allocation,hardware,software architecture,protocols,storage area networks,tcpip
HyperSCSI,Memory bandwidth,Computer science,TCP offload engine,Parallel computing,Server,Multiprocessing,iSCSI,Operating system,Storage area network,Scalability
Conference
ISBN
Citations 
PageRank 
0-7695-2312-9
1
0.38
References 
Authors
10
5
Name
Order
Citations
PageRank
Foong, A.P.118514.14
Gary McAlpine219719.21
david b minturn31078.49
Greg Regnier425822.77
Vikram Saletore5142.03