Title
An on-chip parallel memory architecture for a stereo vision system.
Year
DOI
Venue
2010
10.1109/ICECS.2010.5724557
ICECS
Keywords
Field
DocType
stereo vision,system on chip,image segmentation,logic gates,pattern matching,field programmable gate arrays,parallel systems,fpga,resource utilization,computer vision,chip,component
Logic gate,System on a chip,Stereopsis,Computer science,Field-programmable gate array,Pixel,Cycles per instruction,Computer hardware,Memory architecture,Scalability,Embedded system
Conference
Citations 
PageRank 
References 
1
0.38
6
Authors
2
Name
Order
Citations
PageRank
Andy Motten1143.05
Luc Claesen2606.84