Paper Info
Title
Hardware Support: A Cache Lock Mechanism without Retry
Abstract
A lock mechanism is essential for synchronization on the multiprocessor systems. The conventional queuing lock has two bus traffics that are the initial and retry of the lock-read. This paper proposes the new locking protocol, called WPV (Waiting Processor Variable) lock mechanism, which has only one lock-read bus traffic command. The WPV mechanism accesses the shared data in the initial lock-read phase that is held in the pipelined protocol until the shared data is transferred. The WPV mechanism also uses the cache state lock mechanism to reduce the locking overhead and guarantees the FIFO lock operations in the multiple lock contentions. In this paper, we also derive the analytical model of WPV lock mechanism as well as conventional memory and cache queuing lock mechanisms. The simulation results on the WPV lock mechanism show that about 50% of access time is reduced comparing with the conventional queuing lock mechanism.
Year
DOI
Venue
2005
10.1109/SNPD-SAWN.2005.41
SNPD
Keywords
Field
DocType
fifo lock operation,shared data,multiple lock contention,wpv mechanism,conventional memory,wpv lock mechanism show,hardware support,cache lock mechanism,cache state lock mechanism,wpv lock mechanism,lock mechanism,initial lock-read phase,queueing theory,computer science,protocols,synchronization,hardware,information science,synchronisation
Double-checked locking,Ticket lock,Synchronization,FIFO (computing and electronics),Access time,Lock (computer science),Cache,Computer science,Computer network,Giant lock,Embedded system
Conference
ISBN
Citations 
PageRank 
0-7695-2294-7
0
0.34
References 
Authors
5
3
Name
Order
Citations
PageRank
Chul-Eui Hong1167.74
Kyeongmo Park212.06
Yeong-Tae Song323439.24