Name
Title | ||
|---|---|---|
Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable Core |
Abstract | ||
|---|---|---|
Traditionally SoCs (System on Chip) have been designed using large numbers of processor cores, custom hardware blocks or a combination of both. General purpose processors are usually neither fast nor efficient enough, and designing and testing custom hardware logic is a risky, time consuming endeavor. Configurable, extensible processors are emerging as a viable alternative, as they have characteristics from both design methodologies. Another problem in SoC design is the way these building blocks connect and interact with each other. Network on Chip (NoC) techniques have been proposed to increase flexibility and scalability in SoC design. Two implementations of a signal processing architecture were developed using a configurable processor and NoC techniques, and compared to a custom RTL implementation. Tradeoff between performance, area and flexibility is presented. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ReConFig.2011.64 | ReConFig |
Keywords | Field | DocType |
processor core,general purpose processor,custom rtl implementation,high performance digital signal,configurable core,chip architectures,noc technique,testing custom hardware logic,design methodology,custom hardware block,extensible processor,soc design,configurable processor,logic design,process control,crossbar,digital signal processing,software performance,hardware,network on chip,signal processing,cost analysis,system on chip,parallel processing | Logic synthesis,Signal processing,Digital signal processing,Computer architecture,System on a chip,Computer science,Parallel computing,Network on a chip,Multi-core processor,Crossbar switch,Embedded system,Scalability | Conference |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. C. Pena-Ramos | 1 | 0 | 0.34 |
| R. Parra-Michel | 2 | 23 | 5.19 |