Name
Abstract | ||
|---|---|---|
We present some solutions to handle two problems commonly encountered when dealing with fine grain parallelization on multi-core architecture: Expressing algorithms using a task grain size suitable for the hardware and minimizing the time penalty due to Non Uniform Memory Accesses. To evaluate the benefit of our work we present some experiments on the fine grain parallelization of an iterative solver for sparse linear systems with some comparisons with the Intel TBB approach. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/IPDPSW.2013.204 | Parallel and Distributed Processing Symposium Workshops & PhD Forum |
Keywords | Field | DocType |
sparse linear system,multi-core architecture,iterative solver,intel tbb approach,numa-aware fine grain parallelization,expressing algorithm,non uniform memory accesses,fine grain parallelization,time penalty,task grain size,algorithm design and analysis,grain size,numa,iterative methods,aggregation,parallel processing,computer architecture,programming | Architecture,Linear system,Iterative method,Computer science,Parallel computing,Multicore architecture,Solver | Conference |
ISBN | Citations | PageRank |
978-0-7695-4979-8 | 1 | 0.36 |
References | Authors | |
13 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Corentin Rossignon | 1 | 1 | 0.36 |
| Pascal Henon | 2 | 1 | 0.36 |
| Olivier Aumage | 3 | 160 | 17.10 |
| Samuel Thibault | 4 | 716 | 35.58 |