Title
Optimizing Pairwise Box Intersection Checking on GPUs for Large-Scale Simulations
Abstract
Box intersection checking is a common task used in many large-scale simulations. Traditional methods cannot provide fast box intersection checking with large-scale datasets. This article presents a parallel algorithm to perform Pairwise Box Intersection checking on Graphics processing units (PBIG). The PBIG algorithm consists of three phases: planning, mapping and checking. The planning phase partitions the space into small cells, the sizes of which are determined to optimize performance. The mapping phase maps the boxes into the cells. The checking phase examines the box intersections in the same cell. Several performance optimizations, including load-balancing, output data compression/encoding, and pipelined execution, are presented for the PBIG algorithm. The experimental results show that the PBIG algorithm can process large-scale datasets and outperforms three well-performing algorithms.
Year
DOI
Venue
2013
10.1145/2499913.2499918
ACM Trans. Model. Comput. Simul.
Keywords
Field
DocType
large-scale simulation,box intersection,parallel algorithm,pairwise box intersection checking,fast box intersection checking,optimizing pairwise box intersection,checking phase,box intersection checking,large-scale simulations,well-performing algorithm,large-scale datasets,pbig algorithm,data compression,load balancing
Graphics,Pairwise comparison,Computer science,Parallel algorithm,Load balancing (computing),Parallel computing,Data compression,Encoding (memory)
Journal
Volume
Issue
ISSN
23
3
1049-3301
Citations 
PageRank 
References 
7
0.67
20
Authors
4
Name
Order
Citations
PageRank
Shih-hsiang Lo1376.15
Che-Rung Lee27813.52
I-hsin Chung338832.41
Yeh-Ching Chung498397.16