Name
Title | ||
|---|---|---|
Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures |
Abstract | ||
|---|---|---|
Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our article presents a design methodology and an embedded multicore architecture, focusing on reducing the software design complexity and boosting the performance density. First, we analyze characteristics of the Task-Level Parallelism in modern multimedia workloads. These characteristics are used to formulate requirements for the programming model. Then we translate the programming model requirements to an architecture specification, including a novel low-complexity implementation of cache coherence and a hardware synchronization unit. Our evaluation demonstrates that the novel coherence mechanism substantially simplifies hardware design, while reducing the performance by less than 18% relative to a complex snooping technique. Compared to a single processor core, the multicores have already proven to be more area- and energy-efficient. However, the multicore architectures in embedded systems still compete with highly efficient function-specific hardware accelerators. In this article we identify five architectural methods to boost performance density of multicores; microarchitectural downscaling, asymmetric multicore architectures, multithreading, generic accelerators, and conjoining. Then, we present a novel methodology to explore multicore design spaces, including the architectural methods improving the performance density. The methodology is based on a complex formula computing performances of heterogeneous multicore systems. Using this design space exploration methodology for HD and QuadHD H.264 video decoding, we estimate that the required areas of multicores in CMOS 45 nm are 2.5 mm2 and 8.6 mm2, respectively. These results suggest that heterogeneous multicores are cost-effective for embedded applications and can provide a good programmability support. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2180887.2180890 | ACM Trans. Embedded Comput. Syst. |
Keywords | Field | DocType |
heterogeneous multicore architectures,software design complexity,architectural method,lower hardware design effort,multicore architecture,asymmetric multicore architecture,simplifies hardware design,multicore design space,design space exploration methodology,design methodology,performance density,silicon efficiency,balancing programmability,software design,cache coherence,programming models,processor architecture,cost effectiveness,embedded systems,energy efficient,programming model,multiprocessor,multimedia,hardware accelerator,embedded system | Multithreading,Software design,Computer science,Real-time computing,Multi-core processor,Microarchitecture,Computer architecture,Programming paradigm,Parallel computing,Design space exploration,Cache coherence,Scalability,Embedded system | Journal |
Volume | Issue | ISSN |
11S | 1 | 1539-9087 |
Citations | PageRank | References |
1 | 0.35 | 38 |
Authors | ||
10 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andrei Terechko | 1 | 133 | 8.64 |
| Jan Hoogerbrugge | 2 | 261 | 22.61 |
| Ghiath Alkadi | 3 | 43 | 3.12 |
| Surendra Guntur | 4 | 1 | 0.35 |
| Anirban Lahiri | 5 | 12 | 2.81 |
| Marc Duranton | 6 | 137 | 10.77 |
| Clemens Wüst | 7 | 1 | 0.35 |
| Phillip Christie | 8 | 1 | 0.35 |
| Axel Nackaerts | 9 | 8 | 3.26 |
| Aatish Kumar | 10 | 1 | 0.35 |