Name
Title | ||
|---|---|---|
An area-efficient multistage 3.0- to 8.5-GHz CMOS UWB LNA using tunable active inductors |
Abstract | ||
|---|---|---|
An area-efficient multistage 3.0- to 8.5-GHz ultra-wideband low-noise amplifier (LNA) utilizing tunable active inductors (AIs) is presented. The AI includes a negative impedance circuit (NIC) consisting of a pair of cross-coupled NMOS transistors and is tuned to vary the gain and bandwidth (BW) of the amplifier. Fabricated in a 90-nm digital CMOS process, the proposed fully on-chip LNA occupies a core chip area of only 0.022 mm2. The measurement results show a power gain S21 of 16.0 dB, a noise figure of 3.1-4.4 dB, and an input return loss S11 of less than -10.5 dB over the 3-dB BW of 3.0-8.5 GHz. Tuning the AIs allows one to increase the gain above 18.0 dB and to extend the BW over 9.4 GHz. The LNA consumes 16.0 mW from a power supply of 1.2 V. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCSII.2010.2055990 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
on-chip lna,tunable active inductors,cross-coupled nmos transistor,core chip area,lna consumes,ultra-wideband low-noise amplifier,3-db bw,power supply,power gain s21,area-efficient multistage,cmos uwb lna,90-nm digital cmos process,power gain,chip,ultrawideband,noise figure,inductors,cmos,low noise amplifier,artificial intelligence,bandwidth,impedance,input return loss,active networks | Power gain,Return loss,NMOS logic,Noise figure,Inductor,CMOS,Electronic engineering,Transistor,Electrical engineering,Mathematics,Amplifier | Journal |
Volume | Issue | ISSN |
57 | 8 | 1549-7747 |
Citations | PageRank | References |
8 | 1.11 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Md. Mahbub Reja | 1 | 21 | 2.38 |
| Kambiz Moez | 2 | 8 | 1.44 |
| Igor Filanovsky | 3 | 21 | 8.68 |