Paper Info
Title
Tlsim And Evc: A Term-Level Symbolic Simulator And An Efficient Decision Procedure For The Logic Of Equality With Uninterpreted Functions And Memories
Abstract
We present a tool flow for high-level design and formal verification of embedded processors. The tool flow consists of the term-level symbolic simulator TLSim, the decision procedure EVC (Equality Validity Checker) for the logic of Equality with Uninterpreted Functions and Memories (EUFM), and any SAT solver. TLSim accepts high-level models of a pipelined implementation processor and its non-pipelined specification, as well as a command file indicating how to simulate them symbolically, and produces an EUFM formula for the correctness of the implementation. EVC exploits the property of Positive Equality and other optimisations in order to translate the EUFM formula to an equivalent Boolean formula that can be solved with any SAT procedure. An earlier version of our tool flow was used to formally verify a model of the M center dot CORE processor at Motorola, and detected bugs.
Year
DOI
Venue
2005
10.1504/IJES.2005.008815
INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS
Keywords
Field
DocType
design automation, hardware design languages, logic, microprocessors, simulation, symbolic manipulation
Symbolic simulation,Computer science,Simulation,Correctness,Boolean satisfiability problem,Symbolic computation,Electronic design automation,Processor design,True quantified Boolean formula,Formal verification
Journal
Volume
Issue
ISSN
1
1-2
1741-1068
Citations 
PageRank 
References 
22
0.69
83
Authors
2
Name
Order
Citations
PageRank
Miroslav N. Velev195360.17
Randal E. Bryant292041194.64