Name
Title | ||
|---|---|---|
A High-Throughput On-Chip Variation Monitoring Circuit For Mosfet Threshold Voltage Using Vcdl And Time-To-Digital Converter |
Abstract | ||
|---|---|---|
A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10 mu m and L = 0.18 mu m in a 16 x 16 array matrix fabricated with a 0.18-mu m process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7 mV and 32.2 mV, respectively, for the temperature range from -25 degrees C to 75 degrees C. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10 mV/bit and 3.53 mV/bit at 25 degrees C, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125 ns, which corresponds to the 8-MHz throughput. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1587/transele.E93.C.1333 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | DocType | Volume |
on-chip variation monitoring, threshold voltage, time-to-digital converter (TDC), voltage controlled delay line (VCDL) | Journal | E93C |
Issue | ISSN | Citations |
8 | 0916-8524 | 1 |
PageRank | References | Authors |
0.49 | 2 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jae-Seung Lee | 1 | 58 | 16.02 |
| Jae-yoon Sim | 2 | 508 | 83.58 |
| Hong-june Park | 3 | 465 | 72.93 |