Title
Exploiting "architecture for verification" to streamline the verification process
Abstract
A typical hardware development flow starts the verification process concurrently with RTL, but the overall schedule becomes limited by the effort required to complete all the necessary verification tasks. Being the limiting factor, verification schedules become unpredictable, often resulting in slippage of the tapeout dates. This paper looks at ways to restructure the flow to complete a significant part of this effort during the architectural phase of the project, prior to the start of RTL. This front-loading of the schedule allows a smaller verification team to complete the process with a tighter schedule.
Year
DOI
Venue
2009
10.1145/1629911.1629970
San Francisco, CA
Keywords
DocType
ISSN
typical hardware development flow,necessary verification task,verification process concurrently,verification schedule,overall schedule,smaller verification team,tapeout date,significant part,tighter schedule,architectural phase,data mining,testing,debugging,limiting factor,switches,hardware,job shop scheduling,formal verification,writing,schedules,computer architecture,verification
Conference
0738-100X
ISBN
Citations 
PageRank 
978-1-6055-8497-3
0
0.34
References 
Authors
0
1
Name
Order
Citations
PageRank
Dave Whipp100.34