Name
Abstract | ||
|---|---|---|
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Level Design flow for asynchronous circuits based on Register Transfer Level (RTL) VHDL using commercial simulation and synthesis tools. Contrary to previous asynchronous approaches, the proposed RTL methodology closely resembles familiar synchronous design styles. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1145/370155.370440 | ASP-DAC |
Keywords | Field | DocType |
asynchronous logic,high-level design,complete high level design,familiar synchronous design style,asynchronous circuit,digital design,commercial simulation,available design tool,previous asynchronous approach,ad-hoc methodology,proposed rtl methodology,register transfer level,high level synthesis,intellectual property,logic design,electronics industry,cores,high level design,design methodology,logic circuits,hardware description languages,registers,system on a chip,design flow,logic simulation | Logic synthesis,Asynchronous communication,Computer architecture,Asynchronous system,Computer science,High-level synthesis,Real-time computing,Electronic engineering,Design flow,Logic simulation,Register-transfer level,Asynchronous circuit | Conference |
ISBN | Citations | PageRank |
0-7803-6634-4 | 1 | 0.35 |
References | Authors | |
5 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ross Smith | 1 | 1 | 0.35 |
| Michiel Ligthart | 2 | 65 | 3.88 |