Name
Title | ||
|---|---|---|
Time-area efficient multiplier-free recursive filter architectures for FPGA implementation. |
Abstract | ||
|---|---|---|
Simultaneous design of multiplier-free recursive filters (IIR filters) and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The hardware design methodology leads to high performance recursive filters with sampling frequencies in the interval 15-21 MHz (17 bits internal data representation). It is demonstrated that the time-area efficiency and performance of the architectures are considerably above any known approach. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/ICASSP.1996.550574 | ICASSP |
Keywords | Field | DocType |
xilinx field,multiplier-free recursive filter,hardware design methodology,hardware implementation,fpga implementation,known approach,programmable gate array,simultaneous design,filter architecture,iir filter,high performance recursive filter,time-area efficient multiplier-free recursive,bits internal data representation,band pass filters,hardware,field programmable gate arrays,performance,finite impulse response filter,sampling frequency,field programmable gate array,design methodology,poles and zeros,data representation,transfer functions | Mathematical optimization,Pole–zero plot,Band-pass filter,Computer science,Infinite impulse response,Field-programmable gate array,Multiplier (economics),Transfer function,Recursive filter,Finite impulse response,Computer hardware,Embedded system | Conference |
ISBN | Citations | PageRank |
0-7803-3192-3 | 1 | 0.40 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Shajaan | 1 | 1 | 0.73 |
| J. A. Sorensen | 2 | 79 | 7.83 |