Paper Info
Title
EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture
Abstract
In this study, we developed and implemented a placement and routing algorithm for a new switch-block-free fine-grain reconfigurable device, called MPLD, as an evaluation environment of MPLD's ability to realize sequential circuits. An MPLD consists of an array of multiple-output LUTs (MLUTs), which work as logic elements and/or routing elements, and has no switch blocks for routing, unlike FPGAs. Thus, when the logic cells of a circuit are placed on an MPLD, MLUTs need to be reserved for routing around the placed logic cells. Our simulated annealing-based placement algorithm for MPLDs avoids overcrowding logic cells and reserves routing space, by considering (1) detailed estimated wire congestion and (2) distance between logic cells, in its cost function. In experiments, we confirmed that sequential circuits were successfully placed and routed on MPLDs in our evaluation environment.
Year
DOI
Venue
2011
10.1109/ReConFig.2011.31
ReConFig
Keywords
Field
DocType
detailed estimated wire congestion,overcrowding logic cell,sequential circuit,multiple-output luts,eda environment,simulated annealing-based placement algorithm,logic element,new switch-block-free reconfigurable architecture,cost function,mplds avoids,evaluation environment,logic cell,field programmable gate arrays,logic gate,simulated annealing,place and route,routing,field programmable gate array,fpga,logic gates,sequential circuits,programmable logic devices,placement
Simulated annealing,Architecture,Logic gate,Sequential logic,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Programmable logic device,Routing algorithm
Conference
Citations 
PageRank 
References 
0
0.34
3
Authors
6
Name
Order
Citations
PageRank
M. Nakamura114930.71
Masato Inagi2316.73
Kazuya Tanigawa363.33
Tetsuo Hironaka4149.36
Masayuki Sato521.07
Takashi Ishiguro600.68