Name
Abstract | ||
|---|---|---|
Whilst clock fault attacks are known to be a serious security threat, an in-depth explanation of such faults still seems to be put in order. This work provides a theoretical analysis, backed by practical experiments, explaining when and how clock faults occur. Understanding and modeling the chain of events following a transient clock alteration allows to accurately predict faulty circuit behavior. A prediction fully confirmed by injecting variable-duration faults at predetermined clock cycles. We illustrate the process by successfully attacking an fpga aes implementation using a dll-based fpga platform (one-bit fault attack). |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1007/978-3-642-12510-2_13 | CARDIS |
Keywords | Field | DocType |
clock fault,fpga aes implementation,faulty circuit behavior,variable-duration fault,critical path,dll-based fpga platform,transient clock alteration,in-depth explanation,whilst clock fault attack,one-bit fault attack,clock cycle,delay locked loop,aes | Clock gating,Timing failure,Clock drift,Computer security,Computer science,Clock domain crossing,Real-time computing,Clock skew,Synchronous circuit,Digital clock manager,Cycles per instruction,Embedded system | Conference |
Volume | ISSN | ISBN |
6035 | 0302-9743 | 3-642-12509-3 |
Citations | PageRank | References |
50 | 2.15 | 12 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michel Agoyan | 1 | 87 | 7.51 |
| Jean-Max Dutertre | 2 | 313 | 29.14 |
| David Naccache | 3 | 1920 | 213.34 |
| Bruno Robisson | 4 | 344 | 22.03 |
| Assia Tria | 5 | 296 | 23.36 |