Name
Abstract | ||
|---|---|---|
Run-time assignment of a set of communicating tasks onto a heterogeneous multiprocessor system-on-chip (MP- SoC) platform is a challenging task. Having FPGA fab- ric tiles in such MPSoC platform increases performance and e xibility of the platform. Such FPGA tiles can not only run tasks in hardware but also instantiate a soft IP core that executes the task functionality. Thus fully exploit- ing the available FPGA fabric resources must include ex- ploiting such a hierarchical congur ation. This paper de- tails the benets of using a hierarchical congur ation and illustrates how to incorporate it within a generic run-time task assignment heuristic. We show that adding a hierar- chical congur ation signicantly improves task assignment performance (i.e. success rate and assignment quality). In several cases, the performance of a heuristic with a hier- archical congur ation extends beyond the capabilities of a full solution space exploration without hierarchical cong- uration, at only a fraction of the computation time. |
Year | Venue | Field |
|---|---|---|
2006 | ERSA | Computer architecture,Computer science,Parallel computing,MPSoC |
DocType | Citations | PageRank |
Conference | 1 | 0.39 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vincent Nollet | 1 | 148 | 9.06 |
| Prabhat Avasare | 2 | 226 | 12.97 |
| Diederik Verkest | 3 | 1544 | 123.76 |
| Henk Corporaal | 4 | 1787 | 166.20 |