Name
Abstract | ||
|---|---|---|
We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare favorably with previously published control cir- cuits. We present some results from a chip implementation of several 64-bit domino adders in a TSMC CMOS 180 nm process technology. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ASYNC.2005.21 | Symposium on Asynchronous Circuits and Systems |
Keywords | DocType | ISSN |
gate delay,tsmc cmos,novel asynchronous control circuit,domino circuits,gasp circuit,64-bit domino adder,minimum cycle time,control circuit,nm process technology,chip implementation,gasp control,domino pipeline,cycle time,chip | Conference | 1522-8681 |
ISBN | Citations | PageRank |
0-7695-2305-6 | 3 | 0.45 |
References | Authors | |
9 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jo Ebergen | 1 | 15 | 2.97 |
| Jonathan Gainsley | 2 | 53 | 5.73 |
| Jon K. Lexau | 3 | 209 | 31.97 |
| I. E. Sutherland | 4 | 1520 | 2067.03 |