Name
Abstract | ||
|---|---|---|
A systematic approach to test analog array-processor neural chips is presented. Unique testing problems for analog neural chips are described and effective solutions are discussed. Based on the hierarchical methodology, testing of analog array-processor neural chips can be systematically addressed. The test results for programmable analog neural chips fabricated by a 2-μm CMOS process are presented. These chips contain 25 neurons and 1600 synapses |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1109/ICCD.1991.139859 | Cambridge, MA |
Keywords | Field | DocType |
analog neural array-processor chips,synapses,dynamic range,analog circuits,neural nets,very large scale integration,system testing,cmos integrated circuits,chip,signal processing | Computer science,Electronic engineering,CMOS,Cmos process,Mixed-signal integrated circuit,Vector processor,Artificial neural network | Conference |
ISBN | Citations | PageRank |
0-8186-2270-9 | 1 | 0.40 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wen-Jay Hsu | 1 | 31 | 3.53 |
| Bing J. Sheu | 2 | 115 | 21.86 |
| Sudhir M. Gowda | 3 | 19 | 4.73 |