Paper Info
Title
Logic And Analog Test Schemes For A Single-Chip Pixel-Parallel Fingerprint Identification Lsi
Abstract
This paper describes logic and analog test schemes that improve the testability of a pixel-parallel fingerprint identification circuit. The pixel contains a processing circuit and a capacitive fingerprint sensor circuit. For the logic test, we propose a test method using a pseudo scan circuit to check the processing circuits of all pixels simultaneously. In the analog test. the sensor circuit employs dummy capacitance to mimic the state of a finger touching the chip. This enables an evaluation of the sensitivity of all sensor circuits on logical LSI tester without touching the chip with a finger. To check the effectiveness of the schemes, we applied them to a pixel array in a fingerprint identification LSI. The pseudo scan circuit achieved a 100% failure-detection rate for the processing circuit. The analog test determines that the sensitivities of the sensor circuit in all pixels are in the proper range. The results of the tests confirmed that the proposed schemes can completely detect defects in the circuits. Thus, the schemes will pave the way to logic and analog tests of chips integrating highly functional devices stacked on a LSI.
Year
DOI
Venue
2007
10.1093/ietele/e90-c.10.1892
IEICE TRANSACTIONS ON ELECTRONICS
Keywords
Field
DocType
test, pixel parallel, sensor, fingerprint identification, single chip, high-functional device, MEMS
Automatic test pattern generation,Fingerprint recognition,Circuit extraction,Electronic engineering,Chip,Pixel,Mixed-signal integrated circuit,Engineering,Electronic circuit,Integrated circuit
Journal
Volume
Issue
ISSN
E90C
10
1745-1353
Citations 
PageRank 
References 
1
0.37
0
Authors
8
Name
Order
Citations
PageRank
Satoshi Shigematsu17814.61
Hiroki Morimura2195.16
Toshishige Shimamura332.58
Takahiro Hatano4345.10
Namiko Ikeda521.49
Yukio Okazaki621.15
Katsuyuki Machida7186.81
Mamoru Nakanishi87613.25