Name
Abstract | ||
|---|---|---|
CoHub, a coherency hub ASIC, provides a cost-effective way to extend a glueless two-node chip-multithreading system to a four-node system without changes to the processor. The four-node, 256-thread system achieves near-linear scaling of performance with thread count on transaction-processing workloads. Time-to-market pressure, 800-MHz operation, and a six-stage pipeline were among the constraints that shaped CoHub's design. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/MM.2009.62 | IEEE Micro |
Keywords | Field | DocType |
multi threading,cache coherence,bandwidth,cache coherency,chip,transaction processing,asic design,memory bandwidth,system on chip,coherence,servers,data mining,hardware,application specific integrated circuits,ultrasparc,sun | Multithreading,System on a chip,Memory bandwidth,Computer science,Parallel computing,Server,Real-time computing,Thread (computing),Throughput,UltraSPARC,Cache coherence | Journal |
Volume | Issue | ISSN |
29 | 4 | 0272-1732 |
Citations | PageRank | References |
3 | 0.49 | 1 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| John R. Feehrer | 1 | 20 | 4.42 |
| Paul Rotker | 2 | 4 | 1.24 |
| Milton Shih | 3 | 4 | 1.24 |
| Paul Gingras | 4 | 7 | 1.88 |
| Peter Yakutis | 5 | 7 | 2.32 |
| Stephen Phillips | 6 | 14 | 4.60 |
| John Heath | 7 | 235 | 20.77 |